1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and more particularly, to a semiconductor integrated circuit having an internal circuit and a programmable enabling circuit, in which the internal circuit is enabled or activated by an enabling signal outputted from the programmed enabling circuit.
2. Description of the Prior Art
Conventionally, semiconductor integrated circuits of this sort have been widely used for various semiconductor devices or chips that are enabled or activated by an enabling or chip-selection signal to perform their functions.
For example, with a semiconductor memory device necessitating essentially a large memory space, a lot of semiconductor integrated circuits of this sort are incorporated into the memory device. If all of the integrated circuits thus incorporated in the memory device are always active, the semiconductor memory device will consume a lot of electric power. Then, to decrease the electric power consumption of the memory device, a required one or ones of the incorporated integrated circuits is/are selectively enabled to operate with the use of their enabling or chip-selection signals.
Accordingly, various types of the semiconductor integrated circuits of this sort have been known, in which the enabling (or, chip-selection) circuit is designed to output an enabling signal with a specific "active level" to the internal circuit.
The "active level" is typically defined in such a way that the enabling signal from the enabling circuit may take any one of three logical states, "Low (L)", "High (H)", and "Don't Care" logic states.
If the active level of the enabling signal is set as the low logic state, the internal circuit will be active only when an input signal with the low logic state is applied to the enabling circuit.
If the active level of the enabling signal is set as the high logic state, the internal circuit will be active only when an input signal with the high logic state is applied to the enabling circuit.
If the active level of the enabling signal is set as the Don't Care logic state, the internal circuit will be always active independent of the values or levels of the input signal for the enabling circuit.
The enabling or chip-select circuit is usually programmable according to the customer's or user's requirement.
Examples of the programmable enabling circuit of this sort were disclosed in the U.S. Pat. Nos. 4,612,459 issued in September 1986 and 5,179,540 issued in January 1993.
FIG. 1 shows the example of the enabling circuit for enabling or disabling the operation of an inner circuit, which was disclosed in the U.S. Pat. No. 4,612,459.
As shown in FIG. 1, the conventional programmable enabling circuit includes a NOR circuit 34, an Exclusive OR (EOR) circuit 35, a first programming circuit 36, and a second programming circuit 37.
The first programming circuit 36 is composed of two n-channel Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) N36 and N37. A drain of the MOSFET N36 is applied with a power supply voltage of V.sub.DD. A gate and a source of the MOSFET N36 are coupled together to be connected to a drain of the MOSFET N37. A gate and a source of the MOSFET N37 are coupled together to be connected to the ground. Thus, the two MOSFETs N36 and N37 are serially connected to each other between the voltage level of V.sub.DD and the ground.
The connection point of the gate and source of the MOSFET N36 and the drain of the MOSFET N37 forms a node A', which is connected to an input Y of the NOR circuit 34.
A two-valued input signal IN is applied to another input X of the NOR circuit 34.
The second programing circuit 37 is composed of two n-channel MOSFETs N38 and N39. A drain of the MOSFET N38 is applied with the power supply voltage of V.sub.DD. A gate and a source of the MOSFET N38 are coupled together to be connected to a drain of the MOSFET N39. A gate and a source of the MOSFET N39 are coupled together to be connected to the ground. Thus, the two MOSFETs N38 and N39 are serially connected to each other between the voltage level of V.sub.DD and the ground.
The connection point of the gate and source of the MOSFET N38 and the drain of the MOSFET N39 forms a node B', which is connected to an input Y of the EOR circuit 35.
An output F of the NOR circuit 34 is connected to another input X of the EOR circuit 35. The connection point of the output F of the NOR circuit 34 and the input X of the EOR circuit 35 forms a node C'.
A two-valued output signal OUT of the conventional enabling circuit in FIG. 1, which serves as an enabling signal, is derived from an output F of the EOR circuit 35. This output signal OUT is applied to an input terminal of the inner circuit (not shown) to be enabled.
When an ion-implantation method is used for programming the active level of the input signal IN, the MOSFETs N36, N37, N38, and N39 in the first and second programming circuits 36 and 37 are each fabricated as an enhancement-type (normally-off) one and then, a selected one or ones of them is/are converted to a depletion-type (normally-on) one or ones according to a specific program by an ion-implantation method of a dopant with five valence electrons such as phosphorus (P). The ion-implantation method has been popularly used for fabricating mask Read-Only Memories (ROMs).
The first programming circuit 36 determines the availability for the input signal IN.
If the N-channel MOSFET N36 is converted to a depletion-type one by an ion-implantation method, the voltage or electric potential at the node A' will be at a high (H) level. As a result, the output signal level of the NOR circuit 34, i.e., the voltage level at the node C', will be fixed at a low (L) level.
On the other hand, if the N-channel MOSFET N37 is converted to a depletion-type one by an ion-implantation method, the voltage at the node A' will be at a low level. As a result, when the input signal IN is at a low voltage level, the output signal of the NOR circuit 34 at the node C' will be at a high level. When the input signal IN is at a high voltage level, the output signal level of the NOR circuit 34 at the node C' will be low.
This means that the inner circuit to be enabled by the circuit in FIG. 1 is enabled or disabled according to the level of the input signal IN.
The second programming circuit 37 determines the active level for the internal circuit.
If the N-channel MOSFET N38 is converted to a depletion-type one by an ion-implantation method, the voltage at the node B' will be at a high level. As a result, the voltage of the output signal OUT from the EOR circuit 35 will be at a high or low level when the voltage at the node C' is at a low or high level, respectively.
On the other hand, if the N-channel MOSFET N39 is converted to a depletion-type one by an ion-implantation method, the voltage level at the node B' will be low. As a result, the voltage of the output signal OUT from the EOR circuit 35 will be at a low or high level when the voltage level at the node C' is low or high, respectively.
This means that the active level for the inner circuit is optionally set as high or low according to the programming circuit 37.
Next, the behavior of the conventional enabling circuit in FIG. 1 is explained below with reference to the following TABLE 1, where the characters "D" and "E" denote the "Depletion" type and the "Enhancement" type, respectively.
TABLE 1 __________________________________________________________________________ SIGNAL LEVEL TRANSISTOR TYPE NODE NODE NODE ACTIVE CASE N36 N37 N38 N39 IN A' B' C' OUT LEVEL __________________________________________________________________________ 1 E D D E L L H H L L H L H L H 2 E D E D L L L H H H H L L L L 3 D E E D L H L L L DON'T H H L L L CARE __________________________________________________________________________
Here, it is supposed that the internal circuit is activated when the output signal OUT of the enabling circuit in FIG. 1 is at a low level.
To set the active level of the input signal IN at a low level (Case 1 in TABLE 1), the MOSFET N37 in the first programming circuit 36 and the MOSFET N38 in the second programming circuit 37 are converted to depletion-type ones, respectively. In this case, the voltage or potential at the node A' is at a low level and the voltage at the node B' is at a high level.
Therefore, if the input signal IN is at a low level, the output signal of the NOR circuit 34 (i.e., the voltage at the node C') will be at a high level. Therefore, the output signal OUT from the EOR circuit 35 will be at a low level, enabling the inner circuit (i.e., the inner circuit becomes active).
If the input signal IN is at a high level, the output signal of the NOR circuit 34 (i.e., the voltage at the node C') will be at a low level. Therefore, the output signal OUT from the EOR circuit 35 will be at a high level, disabling the inner circuit (i.e., the inner circuit becomes inactive).
To set the active level of the input signal IN at a high level (Case 2 in TABLE 1), the MOSFET N37 in the first programming circuit 36 and the MOSFET N39 in the second programming circuit 37 are converted to depletion-type ones, respectively. In this case, the voltage at the node A' is at a low level and the voltage at the node B' also is at a low level.
Therefore, if the input signal IN is at a low level, the output signal of the NOR circuit 34 (i.e., the voltage at the node C') will be at a high level. Therefore, the output signal OUT from the EOR circuit 35 will be at a high level, disabling the inner circuit (i.e., the inner circuit becomes inactive).
If the input signal IN is at a high level, the output signal of the NOR circuit 34 (i.e., the voltage at the node C') will be at a low level. Therefore, the output signal OUT from the EOR circuit 35 will be at a low level, enabling the inner circuit (i.e., the inner circuit becomes active).
To set the active level of the input signal IN in a Don't Care condition (Case 3 in TABLE 1), the MOSFET N36 in the first programming circuit 36 and the MOSFET N39 in the second programming circuit 37 are converted to depletion-type ones, respectively. In this case, the voltage at the node A' is at a high level and the voltage at the node B' is at a low level.
Therefore, the output signal of the NOR circuit 34 (i.e., the voltage at the node C') will be fixed at a low level, which is independent of the level of the input signal IN. Therefore, the output signal OUT from the EOR circuit 35 will be always at a low level, enabling always the inner circuit active (i.e., the inner circuit is kept active).
If the input signal IN is at a high level, the output signal of the NOR circuit 34 (i.e., the voltage at the node C') will be at a low level. Therefore, the output signal OUT from the EOR circuit 35 will be at a low level, enabling the inner circuit active (i.e., the inner circuit becomes active).
As explained above, the active level of the input signal IN to the enabling circuit in FIG. 1 is able to be optionally programmed by (a) obtaining a logical sum of the output signal of the first programming circuit 36 and the input signal IN, and then, (b) obtaining an exclusive logical sum of the logical sum thus obtained in the step (a) and the output signal of the second programming circuit 37.
With the conventional enabling circuit in FIG. 1, there are provided with the NOR circuit 34, the EOR circuit 35, and the first and second programming circuits 36 and 37. The NOR circuit 34 needs at least 4 transistors to realize a NOR function and the EOR circuit 35 needs at least 6 transistors to realize a EOR function. Accordingly, the circuit in FIG. 1 needs at least 14 transistors in total for realizing an enabling function.
Additionally, a conventional enabling circuit shown in FIG. 2 in the U.S. Pat. No. 4,612,459 includes 16 transistors, not 14. This is because this circuit includes an Exclusive NOR (ENOR) circuit necessitating at least 8 transistors, instead of an EOR circuit.
To further enhance the integration-scale and device miniaturization in the semiconductor integrated circuit, it has been required to decrease the scale of individual incorporated circuits. From this point of view, the number of necessary transistors needs to be reduced in the enabling circuit of this sort, decreasing the circuit scale.
Further, with the conventional enabling circuit in FIG. 1, the drains of the n-channel MOSFETs N36 and N38 in the first and second programming circuits 36 and 37 are directly connected to the power supply voltage V.sub.DD. Generally, an n-channel MOSFET is lower in withstand voltage than a p-channel MOSFET. As a result, there is a problem that the MOSFETs N36 and N38 tend to be destroyed or damaged due to electrostatic discharge or the like.
To solve this problem, two p-channel MOSFETs may be additionally provided between the MOSFETs N36 and N38 and the power supply voltage level of V.sub.DD, respectively.